Although in principle applicable to any integrated circuits, the present invention and the problems on which it is based are explained with reference to semiconductor structures in silicon technology.
The patterning of semiconductor structures in silicon technology is effected by alternate production of masks, e.g. by exposing and developing photoresist layers, and dry-chemical or wet-chemical isotropic or anisotropic etching. Each lithography step or each lithography level is expensive and complex. Therefore, the aim of semiconductor fabrication is to minimize the number of lithography steps or lithography levels. As well as costs and feature size, another limiting factor in lithographic patterning is the accuracy of the vertical alignment of two or more lithography levels located above one another.
Hitherto, it has been customary for a new photoresist layer to be applied for each level which is to be lithographically patterned and for this photoresist layer to be exposed via a mask and then developed after alignment. Then, after the exposed or unexposed photoresist regions have been removed in the developing process, the semiconductor layer beneath the photoresist mask is patterned by means of a suitable etching process, for example by means of reactive ion etching.